reorganize schematic a bit

add outputs and redo cs

add digipot

schematic for 12V and 5V DACs

begin work on breakout board

BMS rev 13/14 (#55) * Added rev 13 initial swapover * Used rev 12 updated to share locations of resistors * Fixed overlapping traces * Added rev 13 mechancial outline * Improved rev 6 BMS layout * Removed rev13 outline * Created rev 13 and rev 14 that will be modified with the HT05 spring layout * Fixed incorrect datasheet references * Updated routing with rev12 fixes * Updated both schematics and boards to latest library * Added HVD to diagram * Added energy meter * Updated layout * Added frame to rev13 schematic * Added frame to rev14 schematic * Fixed 0 position on silkscreen * Rev13 dimensions adjusted, requries fixes * Rev14 dimensions adjusted, requries fixes * Fixed mounting hole locations, recentered PCB, and fixed 3 spring locations * Fixed more spring locations * BMS rev13 mechanical outline created * Adjusted dimensions of board further * Fixed routing and silkscreen * Minor fixes from today's design review * Removed extra files and started mechanical outlines * Adjusted dimensions + updated mechanical outlines * Moved single transistor pad * Passed DRC and added frames * Ensures board passes JLC DRC

Update .gitignore for LTSpice files (#54) * Update .gitignore * I'm bad at git Co-authored-by: 19etweinstock <19etweinstock@users.noreply.github.com>

Creates license (#39) * Creates license * Update README.md

Update README.md (#53) * Update README.md * fixed one software guide link Co-authored-by: shaand1

HV Board rev 12 (#52) * Work in progress * Adjusted library * Continued routing * Fixing eagle part * Adjusted filter positions * Fixed library part for isolated gate driver * Continuing work * Continuing routing * Finished routing * Adjusting schematic slightly * Removed unnecessary capacitors and added sense for 60V threshold * Removed all values * Working on silkscreen * Added sensing for OKHS * Pull down 60V_THRESHOLD_SIGNAL * HV board rev 12 done * Changed NE Op-amp to generic * Added top copper pour * Adjusted traces slightly * Increased via sizes, fixed silkscreen labels, approved ERC and DRC errors * Fixed one via * Adjusted vias slightly and solved DRC issues * Final * Added HV Spacing * Updating attributes * Started adjusting tolerances * Set cap tolerance to 5% and res tolerance to 1% * Fixed ones skipped * Removed libraries to match master * Updated ref to latest library version * Fixed schematic lack of clarify on STWD100 * Update pull_request_template.md * Added current frames on frames-update branch * Updated sheet descriptions Co-authored-by: yvonneyeh