Files
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PCB / ACC / CIAA_ACC / BANK_0.sch
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PCB / ACC / CIAA_ACC / BANK_112.sch
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PCB / ACC / CIAA_ACC / BANK_500.sch
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PCB / ACC / CIAA_ACC / BANK_501.sch
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PCB / ACC / CIAA_ACC / BANK_502.sch
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PCB / ACC / CIAA_ACC / BANKS_HP.sch
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PCB / ACC / CIAA_ACC / BANKS_HR.sch
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PCB / ACC / CIAA_ACC / ciaa_acc.kicad_pcb
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PCB / ACC / CIAA_ACC / ciaa_acc.sch
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PCB / ACC / CIAA_ACC / Digital_IO.sch
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PCB / ACC / CIAA_ACC / Expansion.sch
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PCB / ACC / CIAA_ACC / FMC-Power.sch
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PCB / ACC / CIAA_ACC / FPGA-Power.sch
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PCB / ACC / CIAA_ACC / OneBank.sch
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PCB / ACC / CIAA_ACC / PMIC.sch
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PCB / ACC / CIAA_ACC / Principal.sch
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PCB / ACC / CIAA_ACC / RTC-HDMI.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / cpu.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / EDU_CIAA_K60.kicad_pcb
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PCB / EDU-FSL / EDU_CIAA_K60 / EDU_CIAA_K60.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / fuente.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / gpio.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / JTAG.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / on_board_io.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / rsS485.sch
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PCB / EDU-FSL / EDU_CIAA_K60 / usb_otg.sch
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PCB / EDU-INTEL / cpu.sch
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PCB / EDU-INTEL / edk.kicad_pcb
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PCB / EDU-INTEL / edk.sch
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PCB / EDU-INTEL / power.sch
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PCB / EDU-INTEL / sd_card.sch
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PCB / EDU-INTEL / usb.sch
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PCB / EDU-NXP / cpu.sch
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PCB / EDU-NXP / edu-ciaa-nxp.kicad_pcb
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PCB / EDU-NXP / edu-ciaa-nxp.sch
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PCB / EDU-NXP / fuente.sch
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PCB / EDU-NXP / gpio.sch
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PCB / EDU-NXP / ON_BOARD_IO.sch
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PCB / EDU-NXP / rsS485_can.sch
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PCB / EDU-NXP / usb.sch
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PCB / EDU-XILINX / ProyectoKicad / Bank14.sch
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PCB / EDU-XILINX / ProyectoKicad / Bank15.sch
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PCB / EDU-XILINX / ProyectoKicad / Bank35.sch
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PCB / EDU-XILINX / ProyectoKicad / EduCiaaX.sch
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PCB / EDU-XILINX / ProyectoKicad / FPGAConfig.sch
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PCB / EDU-XILINX / ProyectoKicad / FPGAPower.sch
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PCB / EDU-XILINX / ProyectoKicad / Power.sch
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PCB / EDU-XILINX / ProyectoKicad / Usb.sch
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PCB / FSL-MINI / CIAA_FSL_MINI.kicad_pcb
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PCB / FSL-MINI / CIAA_FSL_MINI.sch
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PCB / FSL-MINI / cpu.sch
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PCB / FSL-MINI / ethernet.sch
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PCB / FSL-MINI / fuente.sch
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PCB / FSL-MINI / IO.sch
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PCB / FSL-MINI / memories.sch
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PCB / FSL-MINI / usb_otg.sch
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PCB / FSL / CIAA_K60 / analog.sch
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PCB / FSL / CIAA_K60 / analog_out.sch
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PCB / FSL / CIAA_K60 / CIAA_K60.kicad_pcb
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PCB / FSL / CIAA_K60 / CIAA_K60.sch
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PCB / FSL / CIAA_K60 / cpu.sch
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PCB / FSL / CIAA_K60 / din.sch
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PCB / FSL / CIAA_K60 / dout.sch
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PCB / FSL / CIAA_K60 / ethernet.sch
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PCB / FSL / CIAA_K60 / fuente.sch
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PCB / FSL / CIAA_K60 / gpio.sch
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PCB / FSL / CIAA_K60 / JTAG.sch
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PCB / FSL / CIAA_K60 / memories.sch
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PCB / FSL / CIAA_K60 / rsS485_rs232_can.sch
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PCB / FSL / CIAA_K60 / usb_otg.sch
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PCB / NXP / .kicad_pcb.kicad_pcb
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PCB / NXP / analog.sch
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PCB / NXP / analog_out.sch
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PCB / NXP / ciaa-nxp.kicad_pcb
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PCB / NXP / ciaa-nxp.sch
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PCB / NXP / cpu.sch
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PCB / NXP / din.sch
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PCB / NXP / dout.sch
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PCB / NXP / ethernet.sch
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PCB / NXP / fuente.sch
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PCB / NXP / gpio.sch
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PCB / NXP / mem.sch
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PCB / NXP / rsS485_rs232_can.sch
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PCB / NXP / usb_otg.sch
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PCB / PIC / analog.sch
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PCB / PIC / analog_out.sch
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PCB / PIC / ciaa-pic.kicad_pcb
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PCB / PIC / ciaa-pic.sch
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PCB / PIC / cpu.sch
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PCB / PIC / din.sch
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PCB / PIC / dout.sch
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PCB / PIC / ethernet.sch
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PCB / PIC / fuente.sch
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PCB / PIC / gpio.sch
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PCB / PIC / JTAG.sch
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PCB / PIC / mem.sch
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PCB / PIC / rsS485_rs232_can.sch
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PCB / PIC / usb_otg.sch
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PCB / pico / cpu.sch
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PCB / pico / debugger.sch
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PCB / pico / picociaa.kicad_pcb
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PCB / pico / picociaa.sch
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PCB / RX / hw / .kicad_pcb.kicad_pcb
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PCB / RX / hw / analog.sch
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PCB / RX / hw / analog_out.sch
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PCB / RX / hw / ciaa-rx.kicad_pcb
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PCB / RX / hw / ciaa-rx.sch
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PCB / RX / hw / cpu.sch
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PCB / RX / hw / din.sch
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PCB / RX / hw / dout.sch
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PCB / RX / hw / ethernet.sch
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PCB / RX / hw / fuente.sch
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PCB / RX / hw / gpio.sch
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PCB / RX / hw / mem.sch
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PCB / RX / hw / rsS485_rs232_can.sch
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PCB / RX / hw / usb_otg.sch
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PCB / Safety / BUS_ISA.sch
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PCB / Safety / CAN.sch
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PCB / Safety / CIAA_Safety_VTI_1.0.kicad_pcb
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PCB / Safety / CIAA_Safety_VTI_1.0.sch
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PCB / Safety / CPU.sch
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PCB / Safety / ETHERNET.sch
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PCB / Safety / MEM_FLASH_SPI.sch
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PCB / Safety / RM48L952.sch
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PCB / Safety / USB HOST - MEM SD.sch
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PCB / Safety / USB OTG.sch
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PCB / Safety / USB.sch
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PCB / Z3R0 / ciaa-z3r0.kicad_pcb
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PCB / Z3R0 / ciaa-z3r0.sch
Last update 5 years 8 months
by
Noelia Scotti
FilesPCBEDU-INTELbom_scripts | |
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.. | |
bom2csv.xsl | |
bom_csv_grouped_by_value.py | |
bom_cvs.xsl | |
kicad_netlist_reader.py | |
kicad_netlist_reader.pyc | |
python readme.txt |
bom2csv.xsl<!--XSL style sheet to convert EESCHEMA XML Partlist Format to CSV BOM Format Copyright (C) 2013, Stefan Helmert. GPL v2. Functionality: Generation of csv table with table head of all existing field names and correct assigned cell entries How to use this is explained in eeschema.pdf chapter 14. You enter a command line into the netlist exporter using a new (custom) tab in the netlist export dialog. The command is similar to on Windows: xsltproc -o "%O.csv" "C:\Program Files (x86)\KiCad\bin\plugins\bom2csv.xsl" "%I" on Linux: xsltproc -o "%O.csv" /usr/local/lib/kicad/plugins/bom2csv.xsl "%I" Instead of "%O.csv" you can alternatively use "%O" if you will supply your own file extension when prompted in the UI. The double quotes are there to account for the possibility of space(s) in the filename. --> <!-- @package Generate a Tab delimited list (csv file type). One component per line Fields are Ref,Value, Footprint, Datasheet, Field5, Field4, price --> <!DOCTYPE xsl:stylesheet [ <!ENTITY nl "
"> <!--new line CR, LF, or LF, your choice --> ]> <xsl:stylesheet xmlns:xsl="http://www.w3.org/1999/XSL/Transform" version="1.0"> <xsl:output method="text"/> <!-- for table head and empty table fields--> <xsl:key name="headentr" match="field" use="@name"/> <!-- main part --> <xsl:template match="/export"> <xsl:text>Reference, Value, Footprint, Datasheet</xsl:text> <!-- find all existing table head entries and list each one once --> <xsl:for-each select="components/comp/fields/field[generate-id(.) = generate-id(key('headentr',@name)[1])]"> <xsl:text>, </xsl:text> <xsl:value-of select="@name"/> </xsl:for-each> <xsl:text>&nl;</xsl:text> <!-- all table entries --> <xsl:apply-templates select="components/comp"/> </xsl:template> <!-- the table entries --> <xsl:template match="components/comp"> <xsl:value-of select="@ref"/><xsl:text>,</xsl:text> <xsl:value-of select="value"/><xsl:text>,</xsl:text> <xsl:value-of select="footprint"/><xsl:text>,</xsl:text> <xsl:value-of select="datasheet"/> <xsl:apply-templates select="fields"/> <xsl:text>&nl;</xsl:text> </xsl:template> <!-- table entries with dynamic table head --> <xsl:template match="fields"> <!-- remember current fields section --> <xsl:variable name="fieldvar" select="field"/> <!-- for all existing head entries --> <xsl:for-each select="/export/components/comp/fields/field[generate-id(.) = generate-id(key('headentr',@name)[1])]"> <xsl:variable name="allnames" select="@name"/> <xsl:text>,</xsl:text> <!-- for all field entries in the remembered fields section --> <xsl:for-each select="$fieldvar"> <!-- only if this field entry exists in this fields section --> <xsl:if test="@name=$allnames"> <!-- content of the field --> <xsl:value-of select="."/> </xsl:if> <!-- If it does not exist, use an empty cell in output for this row. Every non-blank entry is assigned to its proper column. --> </xsl:for-each> </xsl:for-each> </xsl:template> </xsl:stylesheet>