Files
Last update 5 years 8 months
by
arvalon
Files | |
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.gitignore | |
1.sch | |
1.sch.final.net | |
1.sch.net | |
1.sch.sim | |
1.sch.sim.txt | |
1.sch.sim.txt.proc.log | |
1.sch.simcfg | |
AC_Capasitor.sch | |
AC_Capasitor.sch.simcfg | |
README.md | |
eagle.epf |
1.sch.net* SpiceNetList * * Exported from 1.sch at 31.03.2019 18:32 * * EAGLE Version 9.3.2 Copyright (c) 1988-2019 Autodesk, Inc. * .TEMP=25.000000 * --------- .OPTIONS --------- * --------- .PARAMS --------- * --------- devices --------- V_V1 N_1 0 DC 5V AC 0 PULSE(0 5 0 0 0 7 10) R_R1 N_2 N_3 10K V_VCUR_1 N_1 N_3 C_C1 N_2 0 50u * --------- simulation --------- .print DC V(N_2) V(N_3) I(V_VCUR_1) I(V_V1) .print AC V(N_2) V(N_3) I(V_VCUR_1) I(V_V1) .print TRAN V(N_2) V(N_3) I(V_VCUR_1) I(V_V1) .END