1.sch.final.net
* SpiceNetList
* 
* Exported from 1.sch at 31.03.2019 18:32
* 
* EAGLE Version 9.3.2 Copyright (c) 1988-2019 Autodesk, Inc.
* 
.TEMP=25.0

* --------- .OPTIONS ---------
.OPTIONS ABSTOL=1e-12 GMIN=1e-12 PIVREL=1e-3 ITL1=100 ITL2=50 PIVTOL=1e-13 RELTOL=1e-3 VNTOL=1e-6 CHGTOL=1e-15 ITL4=10 METHOD=TRAP SRCSTEPS=0 TRTOL=7 NODE

* --------- .PARAMS ---------

* --------- devices ---------
V_V1 N_1 0 DC 5V AC 0 PULSE(0 5 0 0 0 7 10) 
R_R1 N_2 N_3 10K 
V_VCUR_1 N_1 N_3 
C_C1 N_2 0 50u 

* --------- simulation ---------


.control
set filetype=ascii
TRAN 0.01 5 0 0.01 
write 1.sch.sim V(N_2) V(N_3) I(V_VCUR_1) I(V_V1)
.endc

.END