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    Last update 6 years 7 months by Gabriel Araujo
    FilesPlacaGPSRevA2Project Outputs for placagps
    ..
    13-JUL-2011
    D30718_10x10.rar
    Design Rule Check - board.drc
    Design Rule Check - board.html
    Design Rule Check - boardBIG.drc
    Design Rule Check - boardBIG.html
    Net Status - board.html
    Net Status - board.txt
    Status Report.Txt
    board.BOM
    board.CSV
    boardBIG-macro.APR_LIB
    boardBIG.DRL
    boardBIG.DRR
    boardBIG.EXTREP
    boardBIG.GBL
    boardBIG.GBO
    boardBIG.GBS
    boardBIG.GD1
    boardBIG.GG1
    boardBIG.GTL
    boardBIG.GTO
    boardBIG.GTS
    boardBIG.LDP
    boardBIG.REP
    boardBIG.RUL
    boardBIG.TXT
    boardBIG.apr
    		 
    Design Rule Check - board.drc
    Protel Design System Design Rule Check
PCB File : C:\Documents and Settings\George\My Documents\Altium\PlacaGPS\RevA2\board.PcbDoc
Date     : 6/14/2011
Time     : 9:02:07 PM

Processing Rule : Room schematic (Bounding Region = (830mil, 790mil, 3529mil, 4750mil) (InComponentClass('schematic'))
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (All),(All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=8mil) (Max=20mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:01
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