Gastd / BIG - Files

Design Rule Check - board.drc
Protel Design System Design Rule Check
PCB File : C:\Documents and Settings\George\My Documents\Altium\PlacaGPS\RevA2\board.PcbDoc
Date     : 6/14/2011
Time     : 9:02:07 PM

Processing Rule : Room schematic (Bounding Region = (830mil, 790mil, 3529mil, 4750mil) (InComponentClass('schematic'))
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=8mil) (All),(All)
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=8mil) (Max=20mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0


Violations Detected : 0
Time Elapsed        : 00:00:01