Files
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PlacaGPS / RevA0 / board.PcbDoc
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PlacaGPS / RevA0 / panel.PcbDoc
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PlacaGPS / RevA0 / schematic.SchDoc
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PlacaGPS / RevA1 / board.PcbDoc
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PlacaGPS / RevA1 / panel.PcbDoc
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PlacaGPS / RevA1 / schematic.SchDoc
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PlacaGPS / RevA1 / Old PcbDoc / board.PcbDoc
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PlacaGPS / RevA1 / Old PcbDoc / boardR.PcbDoc
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PlacaGPS / RevA1 / Old PcbDoc / boardR2.PcbDoc
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PlacaGPS / RevA1 / Old PcbDoc / boardR2_ascii.PcbDoc
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PlacaGPS / RevA2 / board.PcbDoc
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PlacaGPS / RevA2 / boardBIG (backup).PcbDoc
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PlacaGPS / RevA2 / boardBIG.PcbDoc
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PlacaGPS / RevA2 / BoardBig2.PcbDoc
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PlacaGPS / RevA2 / boardOld.PcbDoc
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PlacaGPS / RevA2 / schematic.SchDoc
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PlacaGPS / RevA2 / teste.sch
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PlacaGPS / RevA3 / gps_imu.PcbDoc
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PlacaGPS / RevA3 / gps_imu2.PcbDoc
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PlacaGPS / RevA3 / Sheet1.SchDoc
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PlacaGPS / RevA3 / testemeu.sch
Last update 6 years 7 months
by Gabriel Araujo
Design Rule Check - boardBIG.drcProtel Design System Design Rule Check PCB File : C:\Documents and Settings\George\My Documents\Altium\PlacaGPS\RevA2\boardBIG.PcbDoc Date : 7/15/2011 Time : 11:53:57 AM Processing Rule : Net Antennae (Tolerance=0mil) (All) Rule Violations :0 Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All) Rule Violations :0 Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) Rule Violations :0 Processing Rule : Width Constraint (Min=6mil) (Max=20mil) (Preferred=20mil) (All) Rule Violations :0 Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) Rule Violations :0 Processing Rule : Clearance Constraint (Gap=10mil) (All),(All) Rule Violations :0 Processing Rule : Un-Routed Net Constraint ( (All) ) Rule Violations :0 Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) Rule Violations :0 Processing Rule : Room schematic (Bounding Region = (600mil, 789mil, 831mil, 4771mil) (InComponentClass('schematic')) Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Violation between Room Definition Between Component on TopLayer And Rule on TopLayer Rule Violations :47 Violations Detected : 47 Time Elapsed : 00:00:01