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Last update 4 years 9 months by Dejardin

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CATIA_LiTEDTU-3-pdfjam.pdf
CATIA_LiTEDTU.pdf
LiTE-DTU_v1.2_calib-cache.lib
LiTE-DTU_v1.2_calib.kicad_pcb	view raw
LiTE-DTU_v1.2_calib.kicad_pcb-bak
LiTE-DTU_v1.2_calib.net
LiTE-DTU_v1.2_calib.pro
LiTE-DTU_v1.2_calib.sch	view raw
LiTE-DTU_v1.2_calib.sch-bak
LiTE-DTU_v1.2_calib_bot.png
LiTE-DTU_v1.2_calib_top.png
README.md
WEdirekt_WE68380353-56_PCB.pdf
channel.sch	view raw
channel.sch-bak
fp-info-cache
sym-lib-table

README.md

LiTEDTU_calib project :

Single channel VFE board to test CATIA chip and hopefully working LiTE-DTU.
To be plugged on uLVRB and FEAD boards

M.D.

Initial creation : 2020/05/27 Last Modification : 2020/05/27