updated schematic for readme

board 2.1a

board version 2.1

WIP

updated with new voltage regulator and pwrgd signal for power fail

cleanup clock save config command added default log address/port (need to disable before production ready) remove clock timeing settings from config as they are saved on the ATtiny85 added defined default timezones (compile time options)

remove 4mhz option + small cleanups

added powerfail detection and saving of clock position and state (tick or tock & enababled or not) I2CAnalogClock (ATtiny) now has its config saved

document attiny8 fuse settings set register with PWM_TOP so it can be changed

now ATtiny85 @ 1MHZ