Checked and first cleanup of schematic.
by jackgassett 7 years 6 months
All airwires routed, no drc errors.
by jackgassett 7 years 6 months
Added bypass caps.
by jackgassett 7 years 6 months
Added Power Supply
by jackgassett 7 years 6 months
Route JTAG
by jackgassett 7 years 6 months
Route the rest of the IO pins.
by jackgassett 7 years 6 months
Fixed the names for connector nets
by jackgassett 7 years 6 months
First revision of fpga modules
by jackgassett 7 years 6 months
Report a bug