Version 1.0
by
jackgassett
6 years 1 week
Checked and first cleanup of schematic.
by
jackgassett
6 years 1 week
All airwires routed, no drc errors.
by
jackgassett
6 years 1 week
Added bypass caps.
by
jackgassett
6 years 1 week
Added Power Supply
by
jackgassett
6 years 1 week
Route JTAG
by
jackgassett
6 years 1 week
Route the rest of the IO pins.
by
jackgassett
6 years 1 week
Fixed the names for connector nets
by
jackgassett
6 years 1 week
First revision of fpga modules
by
jackgassett
6 years 2 weeks