Version 1.0
by
jackgassett
6 years 3 weeks
Checked and first cleanup of schematic.
by
jackgassett
6 years 3 weeks
All airwires routed, no drc errors.
by
jackgassett
6 years 3 weeks
Added bypass caps.
by
jackgassett
6 years 3 weeks
Added Power Supply
by
jackgassett
6 years 3 weeks
Route JTAG
by
jackgassett
6 years 3 weeks
Route the rest of the IO pins.
by
jackgassett
6 years 3 weeks
Fixed the names for connector nets
by
jackgassett
6 years 3 weeks
Remove junk from hidden layers
by
jackgassett
6 years 1 month
First revision of fpga modules
by
jackgassett
6 years 1 month
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