Version 1.0
by
jackgassett
7 years 2 months
Checked and first cleanup of schematic.
by
jackgassett
7 years 2 months
All airwires routed, no drc errors.
by
jackgassett
7 years 2 months
Added bypass caps.
by
jackgassett
7 years 2 months
Added Power Supply
by
jackgassett
7 years 2 months
Route JTAG
by
jackgassett
7 years 2 months
Route the rest of the IO pins.
by
jackgassett
7 years 2 months
Fixed the names for connector nets
by
jackgassett
7 years 2 months
Remove junk from hidden layers
by
jackgassett
7 years 3 months
First revision of fpga modules
by
jackgassett
7 years 3 months
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