Create a project on CADLAB.io
Upload PCB design files
View schematics and board layouts
Visual schematic and layout diff
Design annotations
Organizations and project members
GitHub integration
GitHub Chrome extension
Robert Lin
/
VFD clock - Circuit
Create Account
or
Sign In
View history
1
Branches
Branch
master
Files
Discussions
Branches
Close Menu
Help
Scroll
crystalis.brd
Top
Bottom
Pads
Vias
Unrouted
Dimension
tPlace
bPlace
tOrigins
bOrigins
tNames
bNames
tValues
bValues
tStop
bStop
tCream
bCream
tFinish
bFinish
tGlue
bGlue
tTest
bTest
tKeepout
bKeepout
tRestrict
bRestrict
vRestrict
Drills
Holes
Milling
Measures
Document
Reference
tDocu
bDocu
Patch_Top
Vscore
fp3
Name
Beschreib
BGA-Top
BD-Top
fp8
fp9
fp0
LPC17xx
tSilk
Badge_Outline
ReferenceISLANDS
Patch_BOT
_tsilk
_bsilk
tTestmark
bTestmark
_tNames
_bNames
_tValues
_bValues
Mask
tAdjust
bAdjust
Drill_legend
Notes
HeatSink
_bDocu
Contour
200bmp
203bmp
204bmp
205bmp
206bmp
207bmp
208bmp
209bmp
210bmp
211bmp
212bmp
213bmp
214bmp
215bmp
216bmp
225bmp
226bmp
227bmp
228bmp
229bmp
230bmp
Housing
Edge
cooling
routoute
Revision
9507225f
Anonymous
Write a message
Add Comment
Cancel
Failed loading SVG, please refresh the page.
Annotations
Annotate
Show resolved
There are no annotations yet
Report a bug