Files
Last update 3 months 3 days
by LluísPujadasPrat
| FilesVERSIOFINAL1HUELLASLIB_IRLR2905TRPBFIRLR2905TRPBFDEHDLirlr2905trpbf | |
|---|---|
| .. | |
| chips | |
| part_table | |
| sym_1 |
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Create a project on CADLAB.io -
Upload PCB design files -
View schematics and board layouts -
Visual schematic and layout diff -
Design annotations -
Organizations and project members -
GitHub integration -
GitHub Chrome extension