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Design Rule Check - Portable-Psu-PCB.drc
Protel Design System Design Rule Check PCB File : C:\Users\DarrenWinter\Documents\Portable-Power-Supply_1\Portable-Psu-PCB.PcbDoc Date : 31/12/2024 Time : 11:51:42 Processing Rule : Clearance Constraint (Gap=0.2mm) (All),(All) Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U12-(117.39mm,76.175mm) on Top Layer And Via (117.8mm,75.675mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U12-(117.39mm,76.175mm) on Top Layer And Via (117.8mm,76.675mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U12-(118.21mm,76.175mm) on Top Layer And Via (117.8mm,75.675mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U12-(118.21mm,76.175mm) on Top Layer And Via (117.8mm,76.675mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.198mm < 0.2mm) Between Pad U14-2(154.75mm,61.71mm) on Top Layer And Track (154.247mm,61.75mm)(154.25mm,61.748mm) on Top Layer Violation between Clearance Constraint: (0.198mm < 0.2mm) Between Pad U14-2(154.75mm,61.71mm) on Top Layer And Track (154.25mm,61.71mm)(154.25mm,61.748mm) on Top Layer Violation between Clearance Constraint: (0.198mm < 0.2mm) Between Pad U14-2(154.75mm,61.71mm) on Top Layer And Track (155.25mm,60.75mm)(155.25mm,61.71mm) on Top Layer Violation between Clearance Constraint: (0.198mm < 0.2mm) Between Pad U14-4(155.75mm,61.71mm) on Top Layer And Track (155.25mm,60.75mm)(155.25mm,61.71mm) on Top Layer Violation between Clearance Constraint: (0.198mm < 0.2mm) Between Pad U14-9(156.75mm,64.791mm) on Top Layer And Track (157.25mm,64.791mm)(157.25mm,65.124mm) on Top Layer Violation between Clearance Constraint: (Collision < 0.2mm) Between Pad U16-(117.58mm,49.275mm) on Top Layer And Track (116.515mm,49.275mm)(117.99mm,49.275mm) on Top Layer Violation between Clearance Constraint: (0.195mm < 0.2mm) Between Pad U16-(117.58mm,49.275mm) on Top Layer And Track (117.99mm,47.485mm)(117.99mm,48.437mm) on Top Layer Violation between Clearance Constraint: (0.195mm < 0.2mm) Between Pad U16-(117.58mm,49.275mm) on Top Layer And Track (117.99mm,50.135mm)(117.99mm,51.425mm) on Top Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U16-(117.58mm,49.275mm) on Top Layer And Via (117.99mm,48.437mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U16-(117.58mm,49.275mm) on Top Layer And Via (117.99mm,50.135mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.195mm < 0.2mm) Between Pad U16-(118.4mm,49.275mm) on Top Layer And Track (116.515mm,49.275mm)(117.99mm,49.275mm) on Top Layer Violation between Clearance Constraint: (0.195mm < 0.2mm) Between Pad U16-(118.4mm,49.275mm) on Top Layer And Track (117.99mm,47.485mm)(117.99mm,48.437mm) on Top Layer Violation between Clearance Constraint: (0.195mm < 0.2mm) Between Pad U16-(118.4mm,49.275mm) on Top Layer And Track (117.99mm,50.135mm)(117.99mm,51.425mm) on Top Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U16-(118.4mm,49.275mm) on Top Layer And Via (117.99mm,48.437mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.045mm < 0.2mm) Between Pad U16-(118.4mm,49.275mm) on Top Layer And Via (117.99mm,50.135mm) from Top Layer to Bottom Layer Violation between Clearance Constraint: (0.175mm < 0.2mm) Between Track (31mm,50.25mm)(36.373mm,50.25mm) on Bottom Layer And Via (32.397mm,50.825mm) from Top Layer to Bottom Layer Rule Violations :20 Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All) Violation between Short-Circuit Constraint: Between Pad U12-(117.39mm,76.175mm) on Top Layer And Pad U12-11(117.8mm,76.175mm) on Top Layer Location : [X = 117.39mm][Y = 76.175mm] Violation between Short-Circuit Constraint: Between Pad U12-(118.21mm,76.175mm) on Top Layer And Pad U12-11(117.8mm,76.175mm) on Top Layer Location : [X = 118.21mm][Y = 76.175mm] Violation between Short-Circuit Constraint: Between Pad U16-(117.58mm,49.275mm) on Top Layer And Pad U16-11(117.99mm,49.275mm) on Top Layer Location : [X = 117.58mm][Y = 49.275mm] Violation between Short-Circuit Constraint: Between Pad U16-(117.58mm,49.275mm) on Top Layer And Track (116.515mm,49.275mm)(117.99mm,49.275mm) on Top Layer Location : [X = 117.58mm][Y = 49.275mm] Violation between Short-Circuit Constraint: Between Pad U16-(118.4mm,49.275mm) on Top Layer And Pad U16-11(117.99mm,49.275mm) on Top Layer Location : [X = 118.4mm][Y = 49.275mm] Rule Violations :5 Processing Rule : Un-Routed Net Constraint ( (All) ) Rule Violations :0 Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No) Rule Violations :0 Processing Rule : Width Constraint (Min=0.2mm) (Max=1816.048mm) (Preferred=0.3mm) (All) Rule Violations :0 Processing Rule : Routing Topology Rule(Topology=Shortest) (All) Rule Violations :0 Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (InPadClass('PowerPads')) Rule Violations :0 Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.3mm) (Conductor Width=0.102mm) (Air Gap=0.102mm) (Entries=4) (All) Rule Violations :0 Processing Rule : Minimum Annular Ring (Minimum=0.076mm) (All) Rule Violations :0 Processing Rule : Hole Size Constraint (Min=0.2mm) (Max=6.3mm) (All) Rule Violations :0 Processing Rule : Hole To Hole Clearance (Gap=0.25mm) (All),(All) Rule Violations :0 Processing Rule : Minimum Solder Mask Sliver (Gap=0mm) (All),(All) Rule Violations :0 Processing Rule : Silk To Solder Mask (Clearance=0.102mm) (IsPad),(All) Rule Violations :0 Processing Rule : Silk to Silk (Clearance=0mm) (All),(All) Rule Violations :0 Processing Rule : Net Antennae (Tolerance=0mm) (All) Rule Violations :0 Processing Rule : Board Clearance Constraint (Gap=0mm) (All) Rule Violations :0 Processing Rule : Height Constraint (Min=0mm) (Max=1816.048mm) (Prefered=12.7mm) (All) Rule Violations :0 Violations Detected : 25 Waived Violations : 0 Time Elapsed : 00:00:01

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