Prepare for fabrication and assembly in PCBWay
by A zisi 1 year 1 month
Prepare for fabrication and assembly in PCBWay

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
4428ef3f
Add more convinient test pads for RX clock LVDS
by A zisi 1 year 1 month
Add more convinient test pads for RX clock LVDS

Fixes #74

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
9cf69231
Update FPGA-TCXO P/N
by A zisi 1 year 1 month
Update FPGA-TCXO P/N

Fixes #71

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
4e00d740
Expose TRX control pins to FPGA
by A zisi 1 year 1 month
Expose TRX control pins to FPGA

Fixes #94

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
4f2f5a59
Route FPGA pins to PQ9ish header
by A zisi 1 year 1 month
Route FPGA pins to PQ9ish header

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
7ecc09d6
Add load switch in PCB
by A zisi 1 year 1 month
Add load switch in PCB

Fixes #78

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
796d00bb
Migrate to KiCAD 8
by A zisi 1 year 2 months
Migrate to KiCAD 8

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
065152f3
Add dimensions for B2B connector
by A zisi 1 year 7 months
Add dimensions for B2B connector

Fixes #103

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
c1450cce
Include in JTAG connector the debug pins
by A zisi 1 year 7 months
Include in JTAG connector the debug pins

Fixes #72

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
ff55cb6f
Change the NOR memory to one with smaller package
by A zisi 1 year 7 months
Change the NOR memory to one with smaller package

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
737329c2
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