Mikołaj Sowiński / Kasli SoC - History

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    Outjob added.
    by Filip Świtakowski 5 years 8 months
    Changes
    Files
    e209f938
    Schematics cleanup. Added variants.
    by Filip Świtakowski 5 years 9 months
    Changes
    Files
    63ca1e7f
    Layout improvements.
    by Filip Świtakowski 5 years 9 months
    Changes
    Files
    eed1b3cb
    Final routing.
    by Filip Świtakowski 5 years 9 months
    Changes
    Files
    b967030c
    Preliminary routing
    by Filip Świtakowski 5 years 9 months
    Changes
    Files
    e689bce5
    Final placement
    by Filip Świtakowski 5 years 9 months
    Changes
    Files
    035c4aad
    Pin swapping in EXT connectors.
    by Filip Świtakowski 5 years 10 months
    Changes
    Files
    74104524
    Preliminary placement
    by Filip Świtakowski 5 years 10 months
    Changes
    Files
    8a398244
    Changed J24 to PL UART #19
    by Filip Świtakowski 5 years 11 months
    Changes
    Files
    02639e3d
    Changed Rx/Tx UART voltage to 1.8
    by Filip Świtakowski 5 years 11 months
    Changed Rx/Tx UART voltage to 1.8
    Added VREF_DDR and VTT_DDT regulator
    removed IC12
    P5V0_CLK-->chabged to P3V6
    Added DOONE pullup
    removed FPGA ref.
    Added 0R res to TPSA7200RGW to configuration pins.
    Added power budget, ETH chip
    Removed Power controller.
    changes in Zynq POR and SRST.
    Clock signals routed to Clock pins.
    Changes
    Files
    6a8d0043
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