Mikołaj Sowiński / Kasli SoC - History

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    v1.0.1rc1
    by Filip Świtakowski 1 year 11 months
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    1f416e77
    Changed speedgrade to -3
    by Filip Świtakowski 3 years 3 months
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    63c775d4
    Fixed issues after design review.
    by Filip Świtakowski 3 years 3 months
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    55d56bfa
    v1.0rc3
    by Filip Świtakowski 3 years 4 months
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    a1f239a8
    v1.0rc2
    by Greg 3 years 4 months
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    cfacad23
    Ethernet, I2C, GPIO_INTx, some LEDs connected to PS.
    by Filip Świtakowski 3 years 8 months
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    fa9ce08d
    power planes changes
    by Filip Świtakowski 4 years 6 days
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    727d7668
    Preliminary placement
    by Filip Świtakowski 4 years 3 months
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    8a398244
    Changed Rx/Tx UART voltage to 1.8
    by Filip Świtakowski 4 years 4 months
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    6a8d0043
    Repo init.
    by Filip Świtakowski 4 years 4 months
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    21582e8f
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