Files
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hardware / 1v0 / PCB / LimeSDR_Mini_1v0_Rounded.PcbDoc
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hardware / 1v0 / PCB / LimeSDR_Mini_1v0_Rounded_panel.PcbDoc
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hardware / 1v0 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v0 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v0 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v0 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v0 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v0 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v0 / Schematics / 07_FPGA.SchDoc
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hardware / 1v0 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v0 / Schematics / 09_Misc.SchDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded.PcbDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded_panel.PcbDoc
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hardware / 1v1 / PCB / LimeSDR_Mini_1v1_Rounded_soldermask.PcbDoc
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hardware / 1v1 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v1 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v1 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v1 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v1 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v1 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v1 / Schematics / 07_FPGA.SchDoc
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hardware / 1v1 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v1 / Schematics / 09_Misc.SchDoc
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hardware / 1v2 / PCB / LimeSDR_Mini_1v2_Rounded.PcbDoc
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hardware / 1v2 / PCB / LimeSDR_Mini_1v2_Rounded_panel.PcbDoc
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hardware / 1v2 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v2 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v2 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v2 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v2 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v2 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v2 / Schematics / 07_FPGA.SchDoc
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hardware / 1v2 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v2 / Schematics / 09_Misc.SchDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded.PcbDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded_old.PcbDoc
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hardware / 1v3 / PCB / LimeSDR_Mini_1v3_Rounded_panel.PcbDoc
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hardware / 1v3 / Schematics / 01_BlockDiagram.SchDoc
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hardware / 1v3 / Schematics / 02_PowerDiagram.SchDoc
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hardware / 1v3 / Schematics / 03_ClockDiagram.SchDoc
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hardware / 1v3 / Schematics / 04_LMS7002M_Misc.SchDoc
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hardware / 1v3 / Schematics / 05_LMS7002M_RF.SchDoc
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hardware / 1v3 / Schematics / 06_LMS7002M_Power.SchDoc
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hardware / 1v3 / Schematics / 07_FPGA.SchDoc
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hardware / 1v3 / Schematics / 08_USB3_0_device.SchDoc
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hardware / 1v3 / Schematics / 09_Misc.SchDoc
Last update 1 year 3 weeks
Embedded Boards Stackup Compatibility - LimeSDR_Mini_1v1_Rounded_panel.txtStackup Compatibility Filename : E:\Saniok\Lime Micro\Lime PCBs\LimeSDR_Mini_1v1\Altium Designer design files\PCB\LimeSDR_Mini_1v1_Rounded_panel.PcbDoc Date : 2017-11-28 Time : 12:33:18 Time Elapsed : 00:00:00 LimeSDR_Mini_1v1_Rounded_panel, LimeSDR_Mini_1v1_Rounded Top (Signal), Top (Signal) L2 (Signal), L2 (Signal) L3 (Signal), L3 (Signal) L4 (Signal), L4 (Signal) L5 (Signal), L5 (Signal) L6 (Signal), L6 (Signal) L7 (Signal), L7 (Signal) Bottom (Signal), Bottom (Signal) Open Layer Stack Manager, Open Layer Stack Manager count : 9