CPLD: Rework timing between ADC, CPLD, SGPIO
by
Jared Boone
6 years 10 months
CPLD: Rework timing between ADC, CPLD, SGPIO
Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).