SM6FBQ / HackRF clone - History

CPLD: Finish fixing up timing re-validation for RX and TX.

CPLD: Tweak ISE tool settings for speed instead of density.

CPLD: Rework timing between ADC, CPLD, SGPIO

Capture ADC and codec clock state with sufficient timing margin.
Increase drive strength on codec clock and invert CPLD capture clock to provide margin for capturing codec clock (I vs. Q channel).

CPLD: Add files for making bitstreams via Makefile.

CPLD: Set default IOSTANDARD to LVCMOS33, remove from UCF.

CPLD: Pull up HOST_SYNC signal, which is usually floating.

HOST_SYNC is only connected to connector P28, and is therefore not driven (left to float) unless connected to some synchronization signal. Pull it up to keep it steady.

In doing so, I had to switch all unused pins to pull-up, and all input-only and tri-state pins to float. All input/tri-state pins except for HOST_SYNC are tied to the microcontroller and can be pulled up there.

PortaPack: Add .SVF of current JEDEC bitstream file.

PortaPack build consumes this file to embed the bitstream into the firmware.