Schematics refactoring: - New sheet reserved to video memory. - Removed video memory parts inside video_generation. - Removed video memory parts inside GPIO. - Generic cleanup to keep all circuits inside each sheet.

CTC, serial clock and main clock

Found vsync frame signal for z80 + minors

Added FDC sheet (WIP), added partial parallel port inout

Serial communication interface

IO addressing space multiplexing and small IO description

Notes and minor fixes

Upgraded to kicad 7

Some steps in bank switching and crtc circuits - crtc pixel clock generator - 2k ram, enabling logic (heavily incomplete) - other 2k ram, annotation regarding data bus

Correction in speaker address annotation