Removed some dangling notes

Schematics refactoring: - New sheet reserved to video memory. - Removed video memory parts inside video_generation. - Removed video memory parts inside GPIO. - Generic cleanup to keep all circuits inside each sheet.

Added FDC sheet (WIP), added partial parallel port inout

Added some missing labels and references

Discovered bank 0 + fixed wrong signals in video gen

Notes and minor fixes

Missing signal in DRAM logic

RAM addressing, including DRAM ras and cas

Found WR signal and fixed RD

Found aux ram CS too. A great discover...