Giulio / ceda-schematics - History

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    Discovered bank 0 + fixed wrong signals in video gen
    by giuliof 1 year 7 months
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    0f26ddb9
    Notes and minor fixes
    by giuliof 1 year 7 months
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    dee060e7
    DRAM: row/column mux, parity generator (partial), memory ICs
    by giuliof 1 year 8 months
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    c1664cfb
    Missing signal in DRAM logic
    by giuliof 1 year 8 months
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    359801f4
    Partial signal renaming
    by giuliof 1 year 8 months
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    2f7bd26e
    RAM addressing, including DRAM ras and cas
    by giuliof 1 year 8 months
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    9c1b16d9
    Z80 halt controls the RUN LED
    by giuliof 1 year 8 months
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    83326d44
    Found WR signal and fixed RD
    by giuliof 1 year 8 months
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    4b96a2f5
    Found aux ram CS too. A great discover...
    by giuliof 1 year 8 months
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    e2284fc5
    Found both ROM CE and OE
    by giuliof 1 year 8 months
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    4c8bed0f
    Report a bug