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README.md

Verilog CAM Readme

For more information and updates: <![CDATA[]]>http://alexforencich.com/wiki/en/verilog/cam/start<![CDATA[]]>

GitHub repository: <![CDATA[]]>https://github.com/alexforencich/verilog-cam<![CDATA[]]>

Introduction

FPGA-independent content addressable memory module.

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