rich27 / pl_payload_control_module_board - History

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    Board is done. Gonna place an order and see if it works.
    by rich27 1 year 10 months
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    b9d74655
    Final edits minus werid unconnect point on DRC
    by Luis Yon 1 year 10 months
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    2731d690
    Added all edits minus buffer feedback edit
    by Luis Yon 1 year 10 months
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    0aade33d
    Resolving error
    by Luis Yon 1 year 10 months
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    974c7549
    Made power traces thicker(0.4mm and 0.3mm). Added GND vias b/w traces
    by Kylie Angel 1 year 10 months
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    5f3fb174
    updated test point footprints. Delted traces to ground vias on top layer and…
    by Kylie Angel 1 year 10 months
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    02c8baf3
    Fixed Reference Designators
    by Kylie Angel 1 year 10 months
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    2b9d7759
    Final CDR Commit
    by Luis Yon 1 year 10 months
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    d04f71bd
    Merge branch 'Rich_Changes_06242022' into 'master'
    by rich27 1 year 10 months
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    18b31e53
    Most of the board is done. Just need to change the layer of the signal lines.
    by rich27 1 year 10 months
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    0ff20119
    Report a bug