rich27 / pl_payload_control_module_board - History

Final edits minus werid unconnect point on DRC

by Luis Yon 3 years 3 months

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2731d690

Added all edits minus buffer feedback edit

by Luis Yon 3 years 3 months

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0aade33d

Resolving error

by Luis Yon 3 years 3 months

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974c7549

Made power traces thicker(0.4mm and 0.3mm). Added ...

by Kylie Angel 3 years 3 months

Made power traces thicker(0.4mm and 0.3mm). Added GND vias b/w traces

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5f3fb174

updated test point footprints. Delted traces to gr...

by Kylie Angel 3 years 3 months

updated test point footprints. Delted traces to ground vias on top layer and added GND pour on top layer with priority zero.

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02c8baf3

Fixed Reference Designators

by Kylie Angel 3 years 3 months

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2b9d7759

Final CDR Commit

by Luis Yon 3 years 4 months

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d04f71bd

Merge branch 'Rich_Changes_06242022' into 'master'

by rich27 3 years 4 months

Merge branch 'Rich_Changes_06242022' into 'master'

PCB Board

See merge request rich27/plpayloadcontrolmoduleboard!6

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18b31e53

Most of the board is done. Just need to change the...

by rich27 3 years 4 months

Most of the board is done. Just need to change the layer of the signal lines.

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0ff20119

Added power planes. I may go back and change the s...

by rich27 3 years 4 months

Added power planes. I may go back and change the stack up as well as the layout for the level shifters.

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4c9fd033