generation of the fabrication files for the accel board

updated the accel footprint

added 0.1uF capacitor to the accel board

Create pcbWay_design_rules.RUL added pcbWay design rules

moved the outline rectangle to mechanical layer 1 The board outline error are now eliminated

added a rectangle shape to form the outline of the board

supress 3D files

changed every blind via to 0.2mm hole size with 0.6 diameter

removed the clearance outline error