Optimised Product Design / Test - History

minor changes to readme text on how to create new project repo from template repo

modified template KiCAD project to use new OptimisedPD titleblock
changed PCB silkscreen text from KBconsulting to OptimisedPD
updated library ref to use new OptimisedPD titleblock

modified readme.md for Optimised Product Design branding
added spaces before/after links as didn't work when clicked in Notepad++

added Signal/GND/PWR names on layer stackup F.Fab drawing

added simple PCB stackup drawing on F.Fab layer
added dimensions on Dwgs.User as example, updated fab text to match

changed differential pair description to use 'Z' rather than 'R' for impedance
KiCAD removed cache library on its own
updated library ref to latest

added fabrication PCB specification text to F.Fab layer
moved board, origins etc to give more space

added silkscreen logo & PCB ID (locally in PCB design, not using footprints)
added GND copper planes on all 4 layers (0.4mm clearance/0.25mm for same-net)
updated library refs
updated template design with library symb/fp library tables from kicad-library submodule

added name & description text for every PCB layer
added defined track widths (0.25mm to 3mm) & via sizes (0.3/0.6mm & 0.5/0.9mm)

added PCB outline for board size 150mm x 100mm with 1.5mm margin
changed board setup and design rules etc...
...changed board type to 4-layer, components both sides, removed Adhesive layers
...set minimum track width/spacing 0.25mm, min via drill/diameter 0.30/0.60mm
...changed all silk/other laters to 0.12mm line thickness, copper to 0.25mm
...changed to require courtyard definitions in footprints
...changed minimum hole to hole to 0.50mm, some web searches say 0.25mm but to be safe
...changed solder mask clearance to 0.065mm, minimum width to 0.10mm as per NCAB DFM best
annotated-netlisted and roughly placed M3 Holes in design after last commit changes
set origin point, auxiliary axis, and layer alignment target at PCB bottom-left