Replaced/added the null logo to the boards.

Added more legend silkscreen to ears.

Fixed pin header 3d models. We had some of the models doubled up or not fully disabled. Now the TH pin headers are all using KiCad V5 3d model locations and are all disabled. This fixes #23

Changed the inline CRESET resestor to 2k2. We need a lower resistor value so that the FTDI chip can reset the FPGA. Using a 10k resistor results in a voltage divider and the 1.65v is too high to assert reset.

Updated BOM and assembly documentation.

Added bars to make reading of zeros easier.

More cleanup and silkscreen work.

Added missing CRESET label on the back of the board.

Silkscreen improvements.

Add an FPGA CRESET jumper. Fixes #9 Adding an in line resistor for the CRESET line from FTDI as well as a jumper that allows access and pulldown of the CRESET line. This allows us to override the CRESET signal from FTDI and force the FPGA chip to stay in reset in cases when we need to access the flash and prevent the FPGA from configuring the FLASH chip. Especially in cases when the FPGA is using the FLASH after the design is loaded and configures the flash into QSPI and other higher bit modes.