Glasgow Embedded / Glasgow - History

    Close Menu
    Help
    Enlarge CY7C thermal vias to 0.3mm to satisfy boar...
    by whitequark 7 years 5 months
    Enlarge CY7C thermal vias to 0.3mm to satisfy board house capabilities.

    DirtyPCBs can only do 12mil+ finished hole.
    Changes
    Files
    434dbef0
    Restore paste layer for back side pads.
    by whitequark 7 years 5 months
    Restore paste layer for back side pads.

    This got clobbered when I disabled it globally in kicad.
    Changes
    Files
    ae857332
    DFM tweaks to MSOP paste and thermal vias.
    by Andrew Wygle 7 years 5 months
    Changes
    Files
    8190114d
    Fix LM3880 EN divider to have correct threshold (t...
    by whitequark 7 years 5 months
    Fix LM3880 EN divider to have correct threshold (thanks @awygle!).
    Changes
    Files
    97c7eef2
    Leave only ADC on Vsense, and connect LDO and FXMA...
    by whitequark 7 years 5 months
    Leave only ADC on Vsense, and connect LDO and FXMA both to Vio.
    Changes
    Files
    e52160d4
    Fix some unconnected nets.
    by whitequark 7 years 5 months
    Changes
    Files
    e33e830a
    Add fiducials.
    by whitequark 7 years 5 months
    Add fiducials.

    Awfully optimistic, I know :)
    Changes
    Files
    703de7a5
    Add explicit pin1 mark for CY7C as the IPC one is ...
    by whitequark 7 years 5 months
    Add explicit pin1 mark for CY7C as the IPC one is obscured by via.
    Changes
    Files
    aa13ed2b
    Remove decoupling capacitor from non-power (WAKEUP...
    by whitequark 7 years 5 months
    Remove decoupling capacitor from non-power (WAKEUP) pin.
    Changes
    Files
    3ea846fa
    Swap INT0 and INT1 to give ~ALERT highest natural ...
    by whitequark 7 years 5 months
    Swap INT0 and INT1 to give ~ALERT highest natural priority.
    Changes
    Files
    b172ac20
    Report a bug