Use async BF polling and tighten timings in hd44780 applet.

Add proper CDC in hd44780 applet. It uses asynchronous logic, and the phase relationship between D and E is not really defined as e.g. the busy flag may go down at any moment.

Add hd44780 applet.

Fix IOPort.__getitem__ invocation without explicit stop index.

Reduce on-FPGA FIFO depth to 128 to improve timing closure. Waste of block RAM... We should only do this on revA.

Improve program-ice40 applet description.

In program-ice40 applet, use math.ceil to calculate timings. Instead of truncating.

Implement default GlasgowApplet.{add_arguments,build,run}.

Relabel CYP→FX2, FPGA→ICE. Fixes #54.

Implement `glasgow flash`. Fixes #37.