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    Fix R16 value.
    by whitequark 7 years 2 months
    Fix R16 value.

    Closes #18.
    Changes
    Files
    ab949d0f
    Fix layer visibility.
    by whitequark 7 years 2 months
    Changes
    Files
    a9274fca
    Add missing SYNCDELAY().
    by whitequark 7 years 2 months
    Changes
    Files
    5732ea24
    Make all endpoints byte-wide to avoid interfering ...
    by whitequark 7 years 2 months
    Make all endpoints byte-wide to avoid interfering with port D.
    Changes
    Files
    28bb2df1
    Actually set the LED_CY pin as output.
    by whitequark 7 years 2 months
    Changes
    Files
    7dfcb300
    Add revA fab pdf.
    by whitequark 7 years 2 months
    Changes
    Files
    77dde5b1
    Use our official VID:PID pair, 20b7:9db1 (yay!)
    by whitequark 7 years 2 months
    Changes
    Files
    fc5d59eb
    Disable FIFO bus while configuring the FPGA.
    by whitequark 7 years 2 months
    Changes
    Files
    683dd4c5
    Add dedicated register read/write code.
    by whitequark 7 years 2 months
    Add dedicated register read/write code.

    This lets us stall EP0 when trying to access a nonexistent register;
    reusing EEPROM code would silently do nothing on errors.
    Changes
    Files
    0e23d13a
    Hook up some registers to I2C inside the FPGA.
    by whitequark 7 years 2 months
    Changes
    Files
    d54b222c
    Report a bug