Add power budgeting.
by
whitequark
7 years 1 week
Add proper RC filter on VCCPLL.
by
whitequark
7 years 1 week
Add analog frontend schematics.
by
whitequark
7 years 1 week
Connect INT0 to FLAGD to get an interrupt triggered by FPGA.
by
whitequark
7 years 1 week
Add stencil alignment holes, fix attribution.
by
whitequark
7 years 1 week
Fix CY7C68013A and MIC5355 footprints.
by
whitequark
7 years 1 week
Added proper VCCPLL bypass.
by
whitequark
7 years 1 week
Added LEDs, TPs, fixed fab layers.
by
whitequark
7 years 1 week