Update to use latest KiCad libraries.

Add laser cut case, with production files.

Add Glasgow revA production files.

Enlarge CY7C thermal vias to 0.3mm to satisfy board house capabilities. DirtyPCBs can only do 12mil+ finished hole.

Restore paste layer for back side pads. This got clobbered when I disabled it globally in kicad.

DFM tweaks to MSOP paste and thermal vias.

Fix LM3880 EN divider to have correct threshold (thanks @awygle!).

Leave only ADC on Vsense, and connect LDO and FXMA both to Vio.

Fix some unconnected nets.

Add fiducials. Awfully optimistic, I know :)