Use our official VID:PID pair, 20b7:9db1 (yay!)

Disable FIFO bus while configuring the FPGA.

Add dedicated register read/write code. This lets us stall EP0 when trying to access a nonexistent register; reusing EEPROM code would silently do nothing on errors.

Hook up some registers to I2C inside the FPGA.

Add revA schematics pdf.

Remove hardware/packages3D/LED_0603_1608Metric_Castellated.{step,wrl}. This is now provided upstream.

Relax clk_if constraint to 30 MHz :/

Update libfx2.

Add licenses (0BSD and Apache-2.0).

Update .gitignore.