kirill9617 / Luna - History

pre r0.2 -- minor improvements and debug fixes

- add silkscreen connector diagrams
- added test points for clock and voltage rails
- moved SPI connectors for reduced via density (DFM)
- added chip select for debug SPI

hardware: fix reversed FPGA leds, 1V1 regulator pinout, silk typo

rev0: implement all of the routing except length matching

rev0: routing: get our routing significnatly more complete :)

rev0: get most of the major routing done

still needs power routing, length matching for the busses,
and routing for the misc control stuff

rev0: throw the parts down so we can get starting routing