Dennis Field / dvk-mx8m-bsb - History

Organize the USB-C, Battery, and Power sheets at the top-level such that the power-flow makes more sense when reading the schematic

Add demultiplexer to uSDHC2 for the uSD and WiFi's SDIO interfaces, include the DEMUX's (TS3A27518E) 24QFN footprint

Begin WiFi+BT M.2 socket circuit, connect the associated USB bus from the hub circuit, determined that the i.MX8M's UART's default POR state is such that CTS is an output and RTS is an input and assigned the signals accordingly

Begin USB 2.0 hub circuit for M.2 modules, remove supervisory/voltage monitor/watchdog circuit since the EmCraft SoM implements it

USB 2.0 hub circuit still needs to be completed.

Modify the boot config pins such that the eMMC is an 8-bit bus, depressing a momentary push button switch during boot causes SD boot, and relevant options

Use the main 18650 battery for the RTC (instead of a coin-cell), include information about which battery has been narrowed down to be the best option (NCR18650BD), remove 2K EEPROM used for the board ID (MAC address) since it won't be used

Have the charge controller IC handle the USB-C DRP PD switch mechanism, notes added on what procedure is required to operate as sink/source and how to swap between these roles

The mainline kernel's TCPM implementation needs to be used in conjunction with the charge controller IC's interface. For example, if the TCPC (PTN5110HQ CC controller) has the USB configured as a sink role then the TCPM (i.MX8M) would read out the CC_STATUS and POWER_STATUS registers of the CC controller IC to know this is the case, and then it (i.MX8M) would configure the charge controller IC accordingly (sink current from VBUS).

Both the CC controller and charge controller's open-drain output interrupt pins are tied together, which means if either of them pull the line low then the i.MX8M needs to check both of their fault registers to determine if a fault has occured on either chip. If the INT pin wasn't pulled low due to a fault then a status update event from either chip may have triggered it, which needs to be determined, as well as the corresponding action taken. These INT pins may need to be separated if the software side is too complex, so long as there's a spare interrupt pins available.

Fast swap is not supported, and is not a requirement.

Include li-ion charge controller PMIC which implements VBAT UVLO, VBAT OVP, input/output OVP & OCP; completely removed the old buck-boost in favor of this fully integrated chip

The BQ25896 may be able to handle the USB-C DRP PD switch all on its own (needs further investigation).

Replace instances of VSYS with VBAT to remove redundancy

In the case where VBAT can drop below 3.3V then it may be required to use a buck-boost in place of the existing buck converter for the 3.3V rail; may need some testing. Using the +5V rail as an input would also work but would introduce additional losses. According to several sources, when a 18650 Li-ion reaches 3.3V it is practically depleted anyway. When the feedback voltage drops below the internal reference voltage the buck converter will be in its "low dropout operation" with a duty cycle of 100%, so the output voltage should closely follow the input voltage.