Dennis Field / dvk-mx8m-bsb - History

In preperation for the final order, re-export all the manufacturing files using the current date and rev number v1.0.0

Add the fab's stackup, panel array working files, and their CPW calculations

Add a TXB0101 logic level translator to the LCD_RESET# signal, the VIH(max) if the LCD's reset pin is 1.8V so the voltage needs to be translated from 3.3V logic down to 1.8V logic

The active TXB0101 level translator is used so that the pin can continue to be externally pulled low by a 10k resistor. The behavior of having this pin supplied with a logic level exceed its maximum rating is unpredictable (could be fine but could also act in unexpected ways). The TXB0101 is already used in the design as U1302, so now there will be 2x of these per board. This also requires two additional 0402 X5R 10V 100nF caps (already have 87 per board of CL05A104MP5NNNC / EmCraft PN: E-CAP-003-01, will now be 89 per board).

Make the ENET_* traces on the top layer 53mils in order to ensure they have a 50Ohm single-ended impedence, move one of the 5V_P bypass caps close to the SoM end of the USB2 diff pair, add meanders to the ENET_TXC, ENET_TX_CTL, ENET_RX_CTL in order to ensure these segments are matched to the long ENET_RXC segment (56.051mm, the rest of the RGMII signals are <10mm skew from this length and don't need adjusting, re-route the SIM card such that UIM-RESET is routed in between UIM-CLK and UIM-DATA as recommended by a BB manufacturer

Add pi-matching circuit to the baseband modem antenna's feedline

The return path for the antenna may have to have a 6.8nH Murata LQG15HN inductor installed on it (cutting the ground trace shorting the pads). The BoM was updated with the new components and everything was reannotated and updated (page 2's caps were out of order).

Update the schematic symbols and footprints after upgrading to KiCad 5.0.0, fix all ERC and DRC violations after the new update/upgrade

Move the charge controller, USB-C TCPC, and RTC to I2C1

Since each of these ICs will be powered at the same time as the SoM regardless of the PWR_EN state, they should share the same I2C bus as the PMIC.

Use I2C3 bus instead of I2C1 bus based on EmCraft's feedback

Now using GPIO5_IO03 (P4.03) to put the class-D op-amp in shutdown and conserve energy when muted, make C1716 near the ETH PHY's DVDDL pin 47 220nF instead of 10uF (EmCraft suggested that this should be 100nF but their's is 220nF, asked why), added a 10k pull-down to PAM2841's ENA pin, added a 100nF cap to the smart card's C1 VCC pin, added a 1uF cap to the haptic motor circuit's 3V3_P rail

Still need to use I2C3 instead of I2C1 according to EmCraft's suggestions.