Thomas Kelly / EagleCAD - History

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    Routed board
    by antscience 7 years 4 days
    Routed board

    Not optimized for size. This is a POC to get an idea of what the minimum size of the board can be
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    c0b977b0
    Full scale board design
    by antscience 7 years 4 days
    Changes
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    21d8bc09
    Merge pull request #3 from WURacing/Sensorpalooza
    by antscience 7 years 5 days
    Merge pull request #3 from WURacing/Sensorpalooza

    Sensorpalooza
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    0cd281b4
    Backlink to CADLAB.io has been added.
    by cadlab-io[bot] 7 years 5 days
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    a015a83c
    Optimized size and solderability
    by antscience 7 years 1 week
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    962871a9
    Size and DRC Optimizations
    by antscience 7 years 1 week
    Size and DRC Optimizations

    Final size: 1.5"x2.5". Might be a little tricky to solder now, but oh well
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    aa7c6ca8
    ERC Compliant
    by antscience 7 years 1 week
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    4463cee0
    Version 2 Board File
    by antscience 7 years 1 week
    Version 2 Board File

    Added in board file. FINAL
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    41b3aac2
    Fixed ERC
    by antscience 7 years 1 week
    Fixed ERC

    Went through ERC and fixed/approved all errors/warnings except for continuity ones. Board needs to be redrawn completely
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    4ba8fc51
    Added SD Card
    by antscience 7 years 1 week
    Added SD Card

    Forgot to add bypass cap to the SD card reader
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    98945fbb
    Report a bug