Dev branches merged into master branch. Optimizing...
by
Nader Nikbakht
7 years 3 months
Dev branches merged into master branch. Optimizing the board routing and
incorporating GFL comments:
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1- top right of AD8224 (pins 12 and 13): don't run a trace under the corner of the chip, as per the data sheet.
2- power bypassing: capacitor placement does not agree with datasheet recommendation (pg 23 § "Power supplies" ¶ 3 sentence 2)
3- via placement for bypass capacitors should be as close as possible to the 0.1uF caps
4- power planes: you could easily use copper pours instead of traces for the copper planes here, I think you could move the few traces on the internal layers around a pour.
5- gain resistor should be as close to pin 2 and 3 as possible, with equal capacitances. I think they could stand to be closer. Maybe rotating the AD8224 90 degrees clockwise would allow for tighter routing of high-impendace low voltage signals, minimizing the chance of noise sources coupling into the system. Be wary during construction of the +-15V hoving right over the elctrode traces. As the wires move w.r.t. the high impedance traces, the capacitance will vary with the motion inducing current flow (and therefore voltage).
6- C6 may block the connector. I would see how much clearance you have and if the bend angle you're hoping for is achievable. (you can look at my boards as an example of what bend angle is possible)
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