moved GCK1 test point
by Michael Ossmann 12 years 2 weeks
a909ca64
forgot to save schematic
by Michael Ossmann 12 years 2 weeks
ca2162da
P28 and P29 reworked, exposed unused SGPIO signals...
by Michael Ossmann 12 years 2 weeks
P28 and P29 reworked, exposed unused SGPIO signals, moved some CPLD JTAG signals to P28
95ffc704
Updated CPLD bitstream with two's complement I/O a...
by Jared Boone 12 years 2 weeks
Updated CPLD bitstream with two's complement I/O and sample ordering fix.
d006ec76
Remove sample-pair reordering in SGPIO interrupt -...
by Jared Boone 12 years 2 weeks
Remove sample-pair reordering in SGPIO interrupt -- CPLD fixes address this.
89eafaa7
Slow down edges of data lines coming from CPLD.
by Jared Boone 12 years 2 weeks
7ef9c1e9
Invert Q channel data coming from MAX5864, since M...
by Jared Boone 12 years 2 weeks
Invert Q channel data coming from MAX5864, since MAX2837 Q differential pair is reversed.
Do conversion from unsigned to two's-compliment inside FPGA.
147f47a3
Changes due to CGU header API changes.
by Jared Boone 12 years 2 weeks
9856ea3d
forgot to save schematic when adding clock signals...
by Michael Ossmann 12 years 2 weeks
forgot to save schematic when adding clock signals to header
db3ef109
silkscreen tweaks
by Michael Ossmann 12 years 2 weeks
06f34523
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