SM6FBQ / HackRF clone - History

Add memory regions for M0 code to live. In the "rom_to_ram" (SPIFI) version, put M0 binary in ROM. In the RAM version, put M0 code in the destination RAM region.

Assembly file that includes M0 binary into a .o to be linked into the M4 binary. There's certainly a more elegant way, but for now...

Add default M0 code that just loops forever, if a project doesn't specify any SRC_M0_[CS] files.

Relocate SGPIO pin configuration -- it only needs to be done once.

Add skip-every-N function to CPLD, where N is controlled by three input pins from the microcontroller.
Updated SGPIO CPLD testbench, as it had fallen a bit out of date.
Add SGPIO API initialization and control of CPLD decimation feature.

Remove CPLD SVF file, as it's not used by anybody (as far as I know).

Another little fix for the two's complement change -- initialize SGPIO data registers to DAC zero values.