Glasgow Embedded / Glasgow - History

revC: minor nudging and tweaking to improve silkscreen around reg area

revC: reposition fiducials, add a third corner, add more for FX2, FPGA

revC: simplify VUSB routing, move input cap to top layer, double vias

revC: remove additional I/O port silkscreen markings

revC: connect Port A 4,6 to extra FPGA I/Os as well as GBUFs

This allows flexibility in using the PLL with or without the pins as
clock inputs.

revC: minor beauty tweaks to routing, redo USB 2.0 diffpairs

I used the same specs as for LVDS (even though those are 100Ω and USB
2.0 is supposed to be 90Ω, it's short enough it won't matter and we're
not doing tight enough fab control for it to make a difference)

Move three refspecs 0.1mm for symmetry against other side.