Altium

Design Rule Verification Report

Date: 22.06.2021
Time: 00:26:41
Elapsed Time: 00:00:02
Filename: C:\Users\Administrator\Documents\WITHFIELD_WORKSPACE\NausicaaLDOAdapter\Nausicaa_LDO_Adapter\AdapterPCB.PcbDoc
Warnings: 0
Rule Violations: 10

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=8mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=10mil) (Max=60mil) (Preferred=15mil) (InNet('+*') OR InNet('GND')) 0
Width Constraint (Min=6mil) (Max=60mil) (Preferred=8mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=6.89mil) (Conductor Width=7.874mil) (Air Gap=7.874mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter <= AsMM(0.45))) 0
Minimum Annular Ring (Minimum=5mil) (((ObjectKind = 'Pad') OR (ObjectKind = 'Via')) And (Layer = 'MultiLayer') And (HoleDiameter > AsMM(0.45))) 0
Hole Size Constraint (Min=9.842mil) (Max=125.984mil) (All) 0
Hole To Hole Clearance (Gap=13.78mil) (All),(All) 10
Minimum Solder Mask Sliver (Gap=1mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) (IsPad),(All) 0
Silk to Silk (Clearance=1mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (All) 0
Height Constraint (Min=0mil) (Max=984.252mil) (Prefered=492.126mil) (All) 0
Total 10

Hole To Hole Clearance (Gap=13.78mil) (All),(All)
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J1-1(1175mil,1907.48mil) on Multi-Layer And Pad J3-1(1175mil,1907.48mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J1-2(1175mil,1828.74mil) on Multi-Layer And Pad J3-2(1175mil,1828.74mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J1-3(1175mil,1750mil) on Multi-Layer And Pad J3-3(1175mil,1750mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J1-4(1175mil,1671.26mil) on Multi-Layer And Pad J3-4(1175mil,1671.26mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J1-5(1175mil,1592.52mil) on Multi-Layer And Pad J3-5(1175mil,1592.52mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J2-1(2300mil,1907.48mil) on Multi-Layer And Pad J4-1(2300mil,1907.48mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J2-2(2300mil,1828.74mil) on Multi-Layer And Pad J4-2(2300mil,1828.74mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J2-3(2300mil,1750mil) on Multi-Layer And Pad J4-3(2300mil,1750mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J2-4(2300mil,1671.26mil) on Multi-Layer And Pad J4-4(2300mil,1671.26mil) on Multi-Layer Pad/Via Touching Holes
Hole To Hole Clearance Constraint: (Collision < 13.78mil) Between Pad J2-5(2300mil,1592.52mil) on Multi-Layer And Pad J4-5(2300mil,1592.52mil) on Multi-Layer Pad/Via Touching Holes
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