Design Rule Verification Report

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.2mm) (All),(All)	0
Clearance Constraint (Gap=0.4mm) (InPoly),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=0.2mm) (Max=2mm) (Preferred=0.2mm) (All)	0
Width Constraint (Min=0.2mm) (Max=0.2mm) (Preferred=0.2mm) ((InNetClass('ETH_RXD') OR InNetClass('ETH_TXD')))	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Hole Size Constraint (Min=0.025mm) (Max=3.5mm) (All)	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0.01mm) (All),(All)	0
Silk To Solder Mask (Clearance=0.01mm) (IsPad),(All)	0
Silk to Silk (Clearance=0.01mm) (All),(All)	0
Net Antennae (Tolerance=0mm) (All)	0
Matched Lengths(Tolerance=0.2mm) (InNetClass('USB_CTRL_2'))	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Total	0