Altium

Design Rule Verification Report

Date: 3/21/2023
Time: 12:17:45 AM
Elapsed Time: 00:00:03
Filename: C:\Users\tpail\Dropbox\Projects\HME\Projects\Toofon\059-PDB\Board Design\PDB\Altium\059-50-006B-INTERMEDIATE BUS CONVERETER\PCB\059-50-006B.PcbDoc
Warnings: 0
Rule Violations: 24

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=6mil) (All),(All) 0
Clearance Constraint (Gap=30mil) (InNetClass('Mounting Holes')),(All) 0
Clearance Constraint (Gap=6mil) (InNet('MH2')),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=6mil) (Max=200mil) (Preferred=10mil) (All) 0
Minimum Annular Ring (Minimum=7mil) (All) 0
Minimum Annular Ring (Minimum=5mil) (IsVia) 0
Hole Size Constraint (Min=10mil) (Max=250mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 15
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (All) 9
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 24

Hole To Hole Clearance (Gap=10mil) (All),(All)
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4481.929mil,651.832mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4503.838mil,598.939mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4503.838mil,704.726mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4556.732mil,577.029mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4556.732mil,726.636mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4609.626mil,598.939mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4609.626mil,704.726mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-1(4556.732mil,651.832mil) on Multi-Layer And Via (4631.535mil,651.832mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4198.465mil,651.832mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4220.374mil,704.726mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4273.268mil,577.029mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4273.268mil,726.636mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4326.162mil,598.939mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4326.162mil,704.726mil) from Top Layer to Bottom Layer
Hole To Hole Clearance Constraint: (9.748mil < 10mil) Between Pad J7-2(4273.268mil,651.832mil) on Multi-Layer And Via (4348.071mil,651.832mil) from Top Layer to Bottom Layer
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Board Clearance Constraint (Gap=0mil) (All)
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text "BOTTOM LAYER - L4" (1130mil,7115mil) on Bottom Layer
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text "BOTTOM OVERLAY" (-925mil,7395mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text "SIGNAL 1 - L2" (1563.193mil,7395mil) on Signal Layer 1
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text "SIGNAL 2 - L3" (1546.532mil,7255mil) on Signal Layer 2
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text "TOP LAYER - L1" (1463.226mil,7535mil) on Top Layer
Board Outline Clearance(Outline Edge): (Collision < 10mil) Between Board Edge And Text "TOP OVERLAY" (-625.097mil,7535mil) on Top Overlay
Board Outline Clearance(Outline Edge): (5.632mil < 10mil) Between Board Edge And Track (4109.882mil,8.132mil)(4109.882mil,724.667mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (5.632mil < 10mil) Between Board Edge And Track (4109.882mil,8.132mil)(4720.118mil,8.132mil) on Bottom Overlay
Board Outline Clearance(Outline Edge): (5.632mil < 10mil) Between Board Edge And Track (4720.118mil,8.132mil)(4720.118mil,724.667mil) on Bottom Overlay
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